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Code

workaround for Xorg-6.8 not saving the surface registers on bigendian

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architectures, patch by Luca Barbato <lu_zero at gentoo.org>


git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@13336 b3059339-0415-0410-9bf9-f77b7e298cf2
This commit is contained in:
faust3 2004-09-14 20:43:39 +00:00
parent bb0ca7d619
commit 6f9cd1674c
1 changed files with 31 additions and 0 deletions
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31
vidix/drivers/radeon_vid.c
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@ -1316,6 +1316,37 @@ static void radeon_vid_stop_video( void )
static void radeon_vid_display_video( void )
{
int bes_flags;
#ifdef WORDS_BIGENDIAN
#if defined(RAGE128)
/* code from gatos */
{
SAVED_CONFIG_CNTL = INREG(CONFIG_CNTL);
OUTREG(CONFIG_CNTL, SAVED_CONFIG_CNTL &
~(APER_0_BIG_ENDIAN_16BPP_SWAP|APER_0_BIG_ENDIAN_32BPP_SWAP));
// printf("saved: %x, current: %x\n", SAVED_CONFIG_CNTL,
// INREG(CONFIG_CNTL));
}
#else
/*code from radeon_video.c*/
{
SAVED_CONFIG_CNTL = INREG(RADEON_SURFACE_CNTL);
/* OUTREG(RADEON_SURFACE_CNTL, (SAVED_CONFIG_CNTL |
RADEON_NONSURF_AP0_SWP_32BPP) & ~RADEON_NONSURF_AP0_SWP_16BPP);
*/
OUTREG(RADEON_SURFACE_CNTL, SAVED_CONFIG_CNTL & ~(RADEON_NONSURF_AP0_SWP_32BPP
| RADEON_NONSURF_AP0_SWP_16BPP));
/*
OUTREG(RADEON_SURFACE_CNTL, (SAVED_CONFIG_CNTL | RADEON_NONSURF_AP0_SWP_32BPP)
& ~RADEON_NONSURF_AP0_SWP_16BPP);
*/
}
#endif
#endif
radeon_fifo_wait(2);
OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK);
radeon_engine_idle();