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Code

CLE266 Vidix driver initial patch by Timothy Lee <timothy@siriushk.com>, doxygen comments by Benjamin Zores <ben@tutuxclan.org>

Browse Source 
git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@13606 b3059339-0415-0410-9bf9-f77b7e298cf2
This commit is contained in:
faust3 2004-10-10 19:22:38 +00:00
parent 13cb3a5c36
commit 7c070e6d50
4 changed files with 1594 additions and 1 deletions
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1
libdha/oth/pci.db
View File

@ -2932,6 +2932,7 @@ d 11063106 VT6105 [Rhine-III] 0
d 11063109 VT8233C PCI to ISA Bridge 0
d 11063112 VT8361 [KLE133] Host Bridge 0
d 11063116 VT8375 [KM266] Host Bridge 0
d 11063122 VT8623 [CLE266 AGP] 0
d 11063128 VT8753 [P4X266 AGP] 0
d 11063133 VT3133 Host Bridge 0
d 11063147 VT8233A ISA Bridge 0

14
vidix/drivers/Makefile
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@ -58,7 +58,13 @@ SIS_OBJS=sis_vid.o sis_bridge.o
SIS_LIBS=-L../../libdha -ldha
SIS_CFLAGS=$(OPTFLAGS) -fPIC -I. -I..
all: $(CYBERBLADE_VID) $(RADEON_VID) $(RAGE128_VID) $(MACH64_VID) $(NVIDIA_VID) $(GENFB_VID) $(MGA_VID) $(MGA_CRTC2_VID) $(PM3_VID) $(SIS_VID)
UNICHROME_VID=unichrome_vid.so
UNICHROME_SRCS=unichrome_vid.c
UNICHROME_OBJS=unichrome_vid.o
UNICHROME_LIBS=-L../../libdha -ldha -lm
UNICHROME_CFLAGS=$(OPTFLAGS) -fPIC -I. -I..
all: $(CYBERBLADE_VID) $(RADEON_VID) $(RAGE128_VID) $(MACH64_VID) $(NVIDIA_VID) $(GENFB_VID) $(MGA_VID) $(MGA_CRTC2_VID) $(PM3_VID) $(SIS_VID) $(UNICHROME_VID)
.SUFFIXES: .c .o
@ -125,6 +131,12 @@ $(SIS_OBJS): $(SIS_SRCS)
$(SIS_VID): $(SIS_OBJS)
$(CC) -shared $(SIS_OBJS) $(SIS_LIBS) -Wl,-soname,$(SIS_VID) -o $(SIS_VID)
$(UNICHROME_OBJS): $(UNICHROME_SRCS)
$(CC) -c $(UNICHROME_CFLAGS) -o $@ $<
$(UNICHROME_VID): $(UNICHROME_OBJS)
$(CC) -shared $(UNICHROME_OBJS) $(UNICHROME_LIBS) -Wl,-soname,$(UNICHROME_VID) -o $(UNICHROME_VID)
clean:
rm -f *.o *.so *~

635
vidix/drivers/unichrome_regs.h Normal file
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@ -0,0 +1,635 @@
/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/via/via.h,v 1.5 2004/01/05 00:34:17 dawes Exp $ */
/*
* Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
* Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sub license,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _VIA_H_
#define _VIA_H_ 1
/* Video status flag */
#define VIDEO_SHOW 0x80000000 /*Video on*/
#define VIDEO_HIDE 0x00000000 /*Video off*/
#define VIDEO_MPEG_INUSE 0x08000000 /*Video is used with MPEG */
#define VIDEO_HQV_INUSE 0x04000000 /*Video is used with HQV*/
#define VIDEO_CAPTURE0_INUSE 0x02000000 /*Video is used with CAPTURE 0*/
#define VIDEO_CAPTURE1_INUSE 0x00000000 /*Video is used with CAPTURE 1*/
#define VIDEO_1_INUSE 0x01000000 /*Video 1 is used with software flip*/
#define VIDEO_3_INUSE 0x00000000 /*Video 3 is used with software flip*/
#define MPEG_USE_V1 0x00010000 /*[16] : 1:MPEG use V1, 0:MPEG use V3*/
#define MPEG_USE_V3 0x00000000 /*[16] : 1:MPEG use V1, 0:MPEG use V3*/
#define MPEG_USE_HQV 0x00020000 /*[17] : 1:MPEG use HQV,0:MPEG not use HQV*/
#define MPEG_USE_HW_FLIP 0x00040000 /*[18] : 1:MPEG use H/W flip,0:MPEG use S/W flip*/
#define MPEG_USE_SW_FLIP 0x00000000 /*[18] : 1:MPEG use H/W flip,0:MPEG use S/W flip*/
#define CAP0_USE_V1 0x00001000 /*[12] : 1:Capture 0 use V1, 0:Capture 0 use V3*/
#define CAP0_USE_V3 0x00000000 /*[12] : 1:Capture 0 use V1, 0:Capture 0 use V3*/
#define CAP0_USE_HQV 0x00002000 /*[13] : 1:Capture 0 use HQV,0:Capture 0 not use HQV*/
#define CAP0_USE_HW_FLIP 0x00004000 /*[14] : 1:Capture 0 use H/W flip,0:Capture 0 use S/W flip*/
#define CAP0_USE_CCIR656 0x00008000 /*[15] : 1:Capture 0 use CCIR656,0:Capture 0 CCIR601*/
#define CAP1_USE_V1 0x00000100 /*[ 8] : 1:Capture 1 use V1, 0:Capture 1 use V3*/
#define CAP1_USE_V3 0x00000000 /*[ 8] : 1:Capture 1 use V1, 0:Capture 1 use V3*/
#define CAP1_USE_HQV 0x00000200 /*[ 9] : 1:Capture 1 use HQV,0:Capture 1 not use HQV*/
#define CAP1_USE_HW_FLIP 0x00000400 /*[10] : 1:Capture 1 use H/W flip,0:Capture 1 use S/W flip */
#define SW_USE_V1 0x00000010 /*[ 4] : 1:Capture 1 use V1, 0:Capture 1 use V3 */
#define SW_USE_V3 0x00000000 /*[ 4] : 1:Capture 1 use V1, 0:Capture 1 use V3 */
#define SW_USE_HQV 0x00000020 /*[ 5] : 1:Capture 1 use HQV,0:Capture 1 not use HQV */
/*
#define VIDEO1_INUSE 0x00000010 //[ 4] : 1:Video 1 is used with S/W flip
#define VIDEO1_USE_HQV 0x00000020 //[ 5] : 1:Video 1 use HQV with S/W flip
#define VIDEO3_INUSE 0x00000001 //[ 0] : 1:Video 3 is used with S/W flip
#define VIDEO3_USE_HQV 0x00000002 //[ 1] : 1:Video 3 use HQV with S/W flip
*/
/* H/W registers for Video Engine */
/*
* bus master
*/
#define PCI_MASTER_ENABLE 0x01
#define PCI_MASTER_SCATTER 0x00
#define PCI_MASTER_SINGLE 0x02
#define PCI_MASTER_GUI 0x00
#define PCI_MASTER_VIDEO 0x04
#define PCI_MASTER_INPUT 0x00
#define PCI_MASTER_OUTPUT 0x08
/*
* video registers
*/
#define V_FLAGS 0x00
#define V_CAP_STATUS 0x04
#define V_FLIP_STATUS 0x04
#define V_ALPHA_WIN_START 0x08
#define V_ALPHA_WIN_END 0x0C
#define V_ALPHA_CONTROL 0x10
#define V_CRT_STARTADDR 0x14
#define V_CRT_STARTADDR_2 0x18
#define V_ALPHA_STRIDE 0x1C
#define V_COLOR_KEY 0x20
#define V_ALPHA_STARTADDR 0x24
#define V_CHROMAKEY_LOW 0x28
#define V_CHROMAKEY_HIGH 0x2C
#define V1_CONTROL 0x30
#define V12_QWORD_PER_LINE 0x34
#define V1_STARTADDR_1 0x38
#define V1_STARTADDR_Y1 V1_STARTADDR_1
#define V1_STRIDE 0x3C
#define V1_WIN_START_Y 0x40
#define V1_WIN_START_X 0x42
#define V1_WIN_END_Y 0x44
#define V1_WIN_END_X 0x46
#define V1_STARTADDR_2 0x48
#define V1_STARTADDR_Y2 V1_STARTADDR_2
#define V1_ZOOM_CONTROL 0x4C
#define V1_MINI_CONTROL 0x50
#define V1_STARTADDR_0 0x54
#define V1_STARTADDR_Y0 V1_STARTADDR_0
#define V_FIFO_CONTROL 0x58
#define V1_STARTADDR_3 0x5C
#define V1_STARTADDR_Y3 V1_STARTADDR_3
#define HI_CONTROL 0x60
#define SND_COLOR_KEY 0x64
#define ALPHA_V3_PREFIFO_CONTROL 0x68
#define V1_SOURCE_HEIGHT 0x6C
#define HI_TRANSPARENT_COLOR 0x70
#define V_DISPLAY_TEMP 0x74 /* No use */
#define ALPHA_V3_FIFO_CONTROL 0x78
#define V3_SOURCE_WIDTH 0x7C
#define V3_COLOR_KEY 0x80
#define V1_ColorSpaceReg_1 0x84
#define V1_ColorSpaceReg_2 0x88
#define V1_STARTADDR_CB0 0x8C
#define V1_OPAQUE_CONTROL 0x90 /* To be deleted */
#define V3_OPAQUE_CONTROL 0x94 /* To be deleted */
#define V_COMPOSE_MODE 0x98
#define V3_STARTADDR_2 0x9C
#define V3_CONTROL 0xA0
#define V3_STARTADDR_0 0xA4
#define V3_STARTADDR_1 0xA8
#define V3_STRIDE 0xAC
#define V3_WIN_START_Y 0xB0
#define V3_WIN_START_X 0xB2
#define V3_WIN_END_Y 0xB4
#define V3_WIN_END_X 0xB6
#define V3_ALPHA_QWORD_PER_LINE 0xB8
#define V3_ZOOM_CONTROL 0xBC
#define V3_MINI_CONTROL 0xC0
#define V3_ColorSpaceReg_1 0xC4
#define V3_ColorSpaceReg_2 0xC8
#define V3_DISPLAY_TEMP 0xCC /* No use */
#define V1_STARTADDR_CB1 0xE4
#define V1_STARTADDR_CB2 0xE8
#define V1_STARTADDR_CB3 0xEC
#define V1_STARTADDR_CR0 0xF0
#define V1_STARTADDR_CR1 0xF4
#define V1_STARTADDR_CR2 0xF8
#define V1_STARTADDR_CR3 0xFC
/* Video Capture Engine Registers
* Capture Port 1
*/
#define CAP0_MASKS 0x100
#define CAP1_MASKS 0x104
#define CAP0_CONTROL 0x110
#define CAP0_H_RANGE 0x114
#define CAP0_V_RANGE 0x118
#define CAP0_SCAL_CONTROL 0x11C
#define CAP0_VBI_H_RANGE 0x120
#define CAP0_VBI_V_RANGE 0x124
#define CAP0_VBI_STARTADDR 0x128
#define CAP0_VBI_STRIDE 0x12C
#define CAP0_ANCIL_COUNT 0x130
#define CAP0_MAXCOUNT 0x134
#define CAP0_VBIMAX_COUNT 0x138
#define CAP0_DATA_COUNT 0x13C
#define CAP0_FB_STARTADDR0 0x140
#define CAP0_FB_STARTADDR1 0x144
#define CAP0_FB_STARTADDR2 0x148
#define CAP0_STRIDE 0x150
/* Capture Port 2 */
#define CAP1_CONTROL 0x154
#define CAP1_SCAL_CONTROL 0x160
#define CAP1_VBI_H_RANGE 0x164 /*To be deleted*/
#define CAP1_VBI_V_RANGE 0x168 /*To be deleted*/
#define CAP1_VBI_STARTADDR 0x16C /*To be deleted*/
#define CAP1_VBI_STRIDE 0x170 /*To be deleted*/
#define CAP1_ANCIL_COUNT 0x174 /*To be deleted*/
#define CAP1_MAXCOUNT 0x178
#define CAP1_VBIMAX_COUNT 0x17C /*To be deleted*/
#define CAP1_DATA_COUNT 0x180
#define CAP1_FB_STARTADDR0 0x184
#define CAP1_FB_STARTADDR1 0x188
#define CAP1_STRIDE 0x18C
/* SUBPICTURE Registers */
#define SUBP_CONTROL_STRIDE 0x1C0
#define SUBP_STARTADDR 0x1C4
#define RAM_TABLE_CONTROL 0x1C8
#define RAM_TABLE_READ 0x1CC
/* HQV Registers */
#define HQV_CONTROL 0x1D0
#define HQV_SRC_STARTADDR_Y 0x1D4
#define HQV_SRC_STARTADDR_U 0x1D8
#define HQV_SRC_STARTADDR_V 0x1DC
#define HQV_SRC_FETCH_LINE 0x1E0
#define HQV_FILTER_CONTROL 0x1E4
#define HQV_MINIFY_CONTROL 0x1E8
#define HQV_DST_STARTADDR0 0x1EC
#define HQV_DST_STARTADDR1 0x1F0
#define HQV_DST_STARTADDR2 0x1FC
#define HQV_DST_STRIDE 0x1F4
#define HQV_SRC_STRIDE 0x1F8
/*
* Video command definition
*/
/* #define V_ALPHA_CONTROL 0x210 */
#define ALPHA_WIN_EXPIRENUMBER_4 0x00040000
#define ALPHA_WIN_CONSTANT_FACTOR_4 0x00004000
#define ALPHA_WIN_CONSTANT_FACTOR_12 0x0000c000
#define ALPHA_WIN_BLENDING_CONSTANT 0x00000000
#define ALPHA_WIN_BLENDING_ALPHA 0x00000001
#define ALPHA_WIN_BLENDING_GRAPHIC 0x00000002
#define ALPHA_WIN_PREFIFO_THRESHOLD_12 0x000c0000
#define ALPHA_WIN_FIFO_THRESHOLD_8 0x000c0000
#define ALPHA_WIN_FIFO_DEPTH_16 0x00100000
/* V_CHROMAKEY_LOW 0x228 */
#define V_CHROMAKEY_V3 0x80000000
/* V1_CONTROL 0x230 */
#define V1_ENABLE 0x00000001
#define V1_FULL_SCREEN 0x00000002
#define V1_YUV422 0x00000000
#define V1_RGB32 0x00000004
#define V1_RGB15 0x00000008
#define V1_RGB16 0x0000000C
#define V1_YCbCr420 0x00000010
#define V1_COLORSPACE_SIGN 0x00000080
#define V1_SRC_IS_FIELD_PIC 0x00000200
#define V1_SRC_IS_FRAME_PIC 0x00000000
#define V1_BOB_ENABLE 0x00400000
#define V1_FIELD_BASE 0x00000000
#define V1_FRAME_BASE 0x01000000
#define V1_SWAP_SW 0x00000000
#define V1_SWAP_HW_HQV 0x02000000
#define V1_SWAP_HW_CAPTURE 0x04000000
#define V1_SWAP_HW_MC 0x06000000
/* #define V1_DOUBLE_BUFFERS 0x00000000 */
/* #define V1_QUADRUPLE_BUFFERS 0x18000000 */
#define V1_EXPIRE_NUM 0x00050000
#define V1_EXPIRE_NUM_A 0x000a0000
#define V1_EXPIRE_NUM_F 0x000f0000 /* jason */
#define V1_FIFO_EXTENDED 0x00200000
#define V1_ON_CRT 0x00000000
#define V1_ON_SND_DISPLAY 0x80000000
#define V1_FIFO_32V1_32V2 0x00000000
#define V1_FIFO_48V1_32V2 0x00200000
/* V12_QWORD_PER_LINE 0x234 */
#define V1_FETCH_COUNT 0x3ff00000
#define V1_FETCHCOUNT_ALIGNMENT 0x0000000f
#define V1_FETCHCOUNT_UNIT 0x00000004 /* Doubld QWORD */
/* V1_STRIDE */
#define V1_STRIDE_YMASK 0x00001fff
#define V1_STRIDE_UVMASK 0x1ff00000
/* V1_ZOOM_CONTROL 0x24C */
#define V1_X_ZOOM_ENABLE 0x80000000
#define V1_Y_ZOOM_ENABLE 0x00008000
/* V1_MINI_CONTROL 0x250 */
#define V1_X_INTERPOLY 0x00000002 /* X interpolation */
#define V1_Y_INTERPOLY 0x00000001 /* Y interpolation */
#define V1_YCBCR_INTERPOLY 0x00000004 /* Y, Cb, Cr all interpolation */
#define V1_X_DIV_2 0x01000000
#define V1_X_DIV_4 0x03000000
#define V1_X_DIV_8 0x05000000
#define V1_X_DIV_16 0x07000000
#define V1_Y_DIV_2 0x00010000
#define V1_Y_DIV_4 0x00030000
#define V1_Y_DIV_8 0x00050000
#define V1_Y_DIV_16 0x00070000
/* V1_STARTADDR0 0x254 */
#define SW_FLIP_ODD 0x08000000
/* V_FIFO_CONTROL 0x258
* IA2 has 32 level FIFO for packet mode video format
* 32 level FIFO for planar mode video YV12. with extension reg 230 bit 21 enable
* 16 level FIFO for planar mode video YV12. with extension reg 230 bit 21 disable
* BCos of 128 bits. 1 level in IA2 = 2 level in VT3122
*/
#define V1_FIFO_DEPTH12 0x0000000B
#define V1_FIFO_DEPTH16 0x0000000F
#define V1_FIFO_DEPTH32 0x0000001F
#define V1_FIFO_DEPTH48 0x0000002F
#define V1_FIFO_DEPTH64 0x0000003F
#define V1_FIFO_THRESHOLD6 0x00000600
#define V1_FIFO_THRESHOLD8 0x00000800
#define V1_FIFO_THRESHOLD12 0x00000C00
#define V1_FIFO_THRESHOLD16 0x00001000
#define V1_FIFO_THRESHOLD24 0x00001800
#define V1_FIFO_THRESHOLD32 0x00002000
#define V1_FIFO_THRESHOLD40 0x00002800
#define V1_FIFO_THRESHOLD48 0x00003000
#define V1_FIFO_THRESHOLD56 0x00003800
#define V1_FIFO_THRESHOLD61 0x00003D00
#define V1_FIFO_PRETHRESHOLD10 0x0A000000
#define V1_FIFO_PRETHRESHOLD12 0x0C000000
#define V1_FIFO_PRETHRESHOLD29 0x1d000000
#define V1_FIFO_PRETHRESHOLD40 0x28000000
#define V1_FIFO_PRETHRESHOLD44 0x2c000000
#define V1_FIFO_PRETHRESHOLD56 0x38000000
#define V1_FIFO_PRETHRESHOLD61 0x3D000000
/* ALPHA_V3_FIFO_CONTROL 0x278
* IA2 has 32 level FIFO for packet mode video format
* 32 level FIFO for planar mode video YV12. with extension reg 230 bit 21 enable
* 16 level FIFO for planar mode video YV12. with extension reg 230 bit 21 disable
* 8 level FIFO for ALPHA
* BCos of 128 bits. 1 level in IA2 = 2 level in VT3122
*/
#define V3_FIFO_DEPTH16 0x0000000F
#define V3_FIFO_DEPTH24 0x00000017
#define V3_FIFO_DEPTH32 0x0000001F
#define V3_FIFO_DEPTH48 0x0000002F
#define V3_FIFO_DEPTH64 0x0000003F
#define V3_FIFO_THRESHOLD8 0x00000800
#define V3_FIFO_THRESHOLD12 0x00000C00
#define V3_FIFO_THRESHOLD16 0x00001000
#define V3_FIFO_THRESHOLD24 0x00001800
#define V3_FIFO_THRESHOLD32 0x00002000
#define V3_FIFO_THRESHOLD40 0x00002800
#define V3_FIFO_THRESHOLD48 0x00003000
#define V3_FIFO_THRESHOLD56 0x00003800
#define V3_FIFO_THRESHOLD61 0x00003D00
#define V3_FIFO_PRETHRESHOLD10 0x0000000A
#define V3_FIFO_PRETHRESHOLD12 0x0000000C
#define V3_FIFO_PRETHRESHOLD29 0x0000001d
#define V3_FIFO_PRETHRESHOLD40 0x00000028
#define V3_FIFO_PRETHRESHOLD44 0x0000002c
#define V3_FIFO_PRETHRESHOLD56 0x00000038
#define V3_FIFO_PRETHRESHOLD61 0x0000003D
#define V3_FIFO_MASK 0x0000007F
#define ALPHA_FIFO_DEPTH8 0x00070000
#define ALPHA_FIFO_THRESHOLD4 0x04000000
#define ALPHA_FIFO_MASK 0xffff0000
#define ALPHA_FIFO_PRETHRESHOLD4 0x00040000
/* IA2 */
#define ColorSpaceValue_1 0x140020f2
#define ColorSpaceValue_2 0x0a0a2c00
#define ColorSpaceValue_1_3123C0 0x13000DED
#define ColorSpaceValue_2_3123C0 0x13171000
/* For TV setting */
#define ColorSpaceValue_1TV 0x140020f2
#define ColorSpaceValue_2TV 0x0a0a2c00
/* V_COMPOSE_MODE 0x298 */
#define SELECT_VIDEO_IF_COLOR_KEY 0x00000001 /* select video if (color key),otherwise select graphics */
#define SELECT_VIDEO3_IF_COLOR_KEY 0x00000020 /* For 3123C0, select video3 if (color key),otherwise select graphics */
#define SELECT_VIDEO_IF_CHROMA_KEY 0x00000002 /* 0x0000000a //select video if (chroma key ),otherwise select graphics */
#define ALWAYS_SELECT_VIDEO 0x00000000 /* always select video,Chroma key and Color key disable */
#define COMPOSE_V1_V3 0x00000000 /* V1 on top of V3 */
#define COMPOSE_V3_V1 0x00100000 /* V3 on top of V1 */
#define COMPOSE_V1_TOP 0x00000000
#define COMPOSE_V3_TOP 0x00100000
#define V1_COMMAND_FIRE 0x80000000 /* V1 commands fire */
#define V3_COMMAND_FIRE 0x40000000 /* V3 commands fire */
#define V_COMMAND_LOAD 0x20000000 /* Video register always loaded */
#define V_COMMAND_LOAD_VBI 0x10000000 /* Video register always loaded at vbi without waiting source flip */
#define V3_COMMAND_LOAD 0x08000000 /* CLE_C0 Video3 register always loaded */
#define V3_COMMAND_LOAD_VBI 0x00000100 /* CLE_C0 Video3 register always loaded at vbi without waiting source flip */
#define SECOND_DISPLAY_COLOR_KEY_ENABLE 0x00010000
/* V3_ZOOM_CONTROL 0x2bc */
#define V3_X_ZOOM_ENABLE 0x80000000
#define V3_Y_ZOOM_ENABLE 0x00008000
/* V3_MINI_CONTROL 0x2c0 */
#define V3_X_INTERPOLY 0x00000002 /* X interpolation */
#define V3_Y_INTERPOLY 0x00000001 /* Y interpolation */
#define V3_YCBCR_INTERPOLY 0x00000004 /* Y, Cb, Cr all interpolation */
#define V3_X_DIV_2 0x01000000
#define V3_X_DIV_4 0x03000000
#define V3_X_DIV_8 0x05000000
#define V3_X_DIV_16 0x07000000
#define V3_Y_DIV_2 0x00010000
#define V3_Y_DIV_4 0x00030000
#define V3_Y_DIV_8 0x00050000
#define V3_Y_DIV_16 0x00070000
/* SUBP_CONTROL_STRIDE 0x3c0 */
#define SUBP_HQV_ENABLE 0x00010000
#define SUBP_IA44 0x00020000
#define SUBP_AI44 0x00000000
#define SUBP_STRIDE_MASK 0x00001fff
#define SUBP_CONTROL_MASK 0x00070000
/* RAM_TABLE_CONTROL 0x3c8 */
#define RAM_TABLE_RGB_ENABLE 0x00000007
/* CAPTURE0_CONTROL 0x310 */
#define C0_ENABLE 0x00000001
#define BUFFER_2_MODE 0x00000000
#define BUFFER_3_MODE 0x00000004
#define BUFFER_4_MODE 0x00000006
#define SWAP_YUYV 0x00000000
#define SWAP_UYVY 0x00000100
#define SWAP_YVYU 0x00000200
#define SWAP_VYUY 0x00000300
#define IN_601_8 0x00000000
#define IN_656_8 0x00000010
#define IN_601_16 0x00000020
#define IN_656_16 0x00000030
#define DEINTER_ODD 0x00000000
#define DEINTER_EVEN 0x00001000
#define DEINTER_ODD_EVEN 0x00002000
#define DEINTER_FRAME 0x00003000
#define VIP_1 0x00000000
#define VIP_2 0x00000400
#define H_FILTER_2 0x00010000
#define H_FILTER_4 0x00020000
#define H_FILTER_8_1331 0x00030000
#define H_FILTER_8_12221 0x00040000
#define VIP_ENABLE 0x00000008
#define EN_FIELD_SIG 0x00000800
#define VREF_INVERT 0x00100000
#define FIELD_INPUT_INVERSE 0x00400000
#define FIELD_INVERSE 0x40000000
#define C1_H_MINI_EN 0x00000800
#define C0_H_MINI_EN 0x00000800
#define C1_V_MINI_EN 0x04000000
#define C0_V_MINI_EN 0x04000000
#define C1_H_MINI_2 0x00000400
/* CAPTURE1_CONTROL 0x354 */
#define C1_ENABLE 0x00000001
/* V3_CONTROL 0x2A0 */
#define V3_ENABLE 0x00000001
#define V3_FULL_SCREEN 0x00000002
#define V3_YUV422 0x00000000
#define V3_RGB32 0x00000004
#define V3_RGB15 0x00000008
#define V3_RGB16 0x0000000C
#define V3_COLORSPACE_SIGN 0x00000080
#define V3_EXPIRE_NUM 0x00040000
#define V3_EXPIRE_NUM_F 0x000f0000
#define V3_BOB_ENABLE 0x00400000
#define V3_FIELD_BASE 0x00000000
#define V3_FRAME_BASE 0x01000000
#define V3_SWAP_SW 0x00000000
#define V3_SWAP_HW_HQV 0x02000000
#define V3_FLIP_HW_CAPTURE0 0x04000000
#define V3_FLIP_HW_CAPTURE1 0x06000000
/* V3_ALPHA_FETCH_COUNT 0x2B8 */
#define V3_FETCH_COUNT 0x3ff00000
#define ALPHA_FETCH_COUNT 0x000003ff
/* HQV_CONTROL 0x3D0 */
#define HQV_RGB32 0x00000000
#define HQV_RGB16 0x20000000
#define HQV_RGB15 0x30000000
#define HQV_YUV422 0x80000000
#define HQV_YUV420 0xC0000000
#define HQV_ENABLE 0x08000000
#define HQV_SRC_SW 0x00000000
#define HQV_SRC_MC 0x01000000
#define HQV_SRC_CAPTURE0 0x02000000
#define HQV_SRC_CAPTURE1 0x03000000
#define HQV_FLIP_EVEN 0x00000000
#define HQV_FLIP_ODD 0x00000020
#define HQV_SW_FLIP 0x00000010 /* Write 1 to flip HQV buffer */
#define HQV_DEINTERLACE 0x00010000 /* First line of odd field will be repeated 3 times */
#define HQV_FIELD_2_FRAME 0x00020000 /* Src is field. Display each line 2 times */
#define HQV_FRAME_2_FIELD 0x00040000 /* Src is field. Display field */
#define HQV_FRAME_UV 0x00000000 /* Src is Non-interleaved */
#define HQV_FIELD_UV 0x00100000 /* Src is interleaved */
#define HQV_IDLE 0x00000008
#define HQV_FLIP_STATUS 0x00000001
#define HQV_DOUBLE_BUFF 0x00000000
#define HQV_TRIPLE_BUFF 0x04000000
#define HQV_SUBPIC_FLIP 0x00008000
#define HQV_FIFO_STATUS 0x00001000
/* HQV_FILTER_CONTROL 0x3E4 */
#define HQV_H_LOWPASS_2TAP 0x00000001
#define HQV_H_LOWPASS_4TAP 0x00000002
#define HQV_H_LOWPASS_8TAP1 0x00000003 /* To be deleted */
#define HQV_H_LOWPASS_8TAP2 0x00000004 /* To be deleted */
#define HQV_H_HIGH_PASS 0x00000008
#define HQV_H_LOW_PASS 0x00000000
#define HQV_V_LOWPASS_2TAP 0x00010000
#define HQV_V_LOWPASS_4TAP 0x00020000
#define HQV_V_LOWPASS_8TAP1 0x00030000
#define HQV_V_LOWPASS_8TAP2 0x00040000
#define HQV_V_HIGH_PASS 0x00080000
#define HQV_V_LOW_PASS 0x00000000
#define HQV_H_HIPASS_F1_DEFAULT 0x00000040
#define HQV_H_HIPASS_F2_DEFAULT 0x00000000
#define HQV_V_HIPASS_F1_DEFAULT 0x00400000
#define HQV_V_HIPASS_F2_DEFAULT 0x00000000
#define HQV_H_HIPASS_F1_2TAP 0x00000050
#define HQV_H_HIPASS_F2_2TAP 0x00000100
#define HQV_V_HIPASS_F1_2TAP 0x00500000
#define HQV_V_HIPASS_F2_2TAP 0x01000000
#define HQV_H_HIPASS_F1_4TAP 0x00000060
#define HQV_H_HIPASS_F2_4TAP 0x00000200
#define HQV_V_HIPASS_F1_4TAP 0x00600000
#define HQV_V_HIPASS_F2_4TAP 0x02000000
#define HQV_H_HIPASS_F1_8TAP 0x00000080
#define HQV_H_HIPASS_F2_8TAP 0x00000400
#define HQV_V_HIPASS_F1_8TAP 0x00800000
#define HQV_V_HIPASS_F2_8TAP 0x04000000
/* IA2 NEW */
#define HQV_V_FILTER2 0x00080000
#define HQV_H_FILTER2 0x00000008
#define HQV_H_TAP2_11 0x00000041
#define HQV_H_TAP4_121 0x00000042
#define HQV_H_TAP4_1111 0x00000401
#define HQV_H_TAP8_1331 0x00000221
#define HQV_H_TAP8_12221 0x00000402
#define HQV_H_TAP16_1991 0x00000159
#define HQV_H_TAP16_141041 0x0000026A
#define HQV_H_TAP32 0x0000015A
#define HQV_V_TAP2_11 0x00410000
#define HQV_V_TAP4_121 0x00420000
#define HQV_V_TAP4_1111 0x04010000
#define HQV_V_TAP8_1331 0x02210000
#define HQV_V_TAP8_12221 0x04020000
#define HQV_V_TAP16_1991 0x01590000
#define HQV_V_TAP16_141041 0x026A0000
#define HQV_V_TAP32 0x015A0000
#define HQV_V_FILTER_DEFAULT 0x00420000
#define HQV_H_FILTER_DEFAULT 0x00000040
/* HQV_MINI_CONTROL 0x3E8 */
#define HQV_H_MINIFY_ENABLE 0x00000800
#define HQV_V_MINIFY_ENABLE 0x08000000
#define HQV_VDEBLOCK_FILTER 0x80000000
#define HQV_HDEBLOCK_FILTER 0x00008000
#define CHROMA_KEY_LOW 0x00FFFFFF
#define CHROMA_KEY_HIGH 0x00FFFFFF
/* V_CAP_STATUS */
#define V_ST_UPDATE_NOT_YET 0x00000003
#define V1_ST_UPDATE_NOT_YET 0x00000001
#define V3_ST_UPDATE_NOT_YET 0x00000008
#define VBI_STATUS 0x00000002
/*
* Macros for Video MMIO
*/
#ifndef V4L2
#define VIDInB(port) *((volatile CARD8 *)(pVia->VidMapBase + (port)))
#define VIDInW(port) *((volatile CARD16 *)(pVia->VidMapBase + (port)))
#define VIDInD(port) *((volatile CARD32 *)(pVia->VidMapBase + (port)))
#define VIDOutB(port, data) *((volatile CARD8 *)(pVia->VidMapBase + (port))) = (data)
#define VIDOutW(port, data) *((volatile CARD16 *)(pVia->VidMapBase + (port))) = (data)
#define VIDOutD(port, data) *((volatile CARD32 *)(pVia->VidMapBase + (port))) = (data)
#define MPGOutD(port, data) *((volatile CARD32 *)(lpMPEGMMIO +(port))) = (data)
#define MPGInD(port) *((volatile CARD32 *)(lpMPEGMMIO +(port)))
#endif
/*
* Macros for GE MMIO
*/
#define GEInW(port) *((volatile CARD16 *)(lpGEMMIO + (port)))
#define GEInD(port) *((volatile CARD32 *)(lpGEMMIO + (port)))
#define GEOutW(port, data) *((volatile CARD16 *)(lpGEMMIO + (port))) = (data)
#define GEOutD(port, data) *((volatile CARD32 *)(lpGEMMIO + (port))) = (data)
/*
* MPEG 1/2 Slice Engine (at 0xC00 relative to base)
*/
#define MPG_CONTROL 0x00
#define MPG_CONTROL_STRUCT 0x03
#define MPG_CONTROL_STRUCT_TOP 0x01
#define MPG_CONTROL_STRUCT_BOTTOM 0x02
#define MPG_CONTROL_STRUCT_FRAME 0x03
/* Use TOP if interlaced */
#define MPG_CONTROL_TYPE 0x3C
#define MPG_CONTROL_TYPE_I (0x01 << 2)
#define MPG_CONTROL_TYPE_B (0x02 << 2)
#define MPG_CONTROL_TYPE_P (0x03 << 3)
#define MPG_CONTROL_ALTSCAN 0x40
#define MPG_BLOCK 0x08 /* Unsure */
#define MPG_COMMAND 0x0C
#define MPG_DATA1 0x10
#define MPG_DATA2 0x14
#define MPG_DATA3 0x18
#define MPG_DATA4 0x1C
#define MPG_YPHYSICAL(x) (0x20 + 12*(x))
#define MPG_CbPHYSICAL(x) (0x24 + 12*(x))
#define MPG_CrPHYSICAL(x) (0x28 + 12*(x))
#define MPG_PITCH 0x50
#define MPG_STATUS 0x54
#define MPG_MATRIX_IDX 0x5C
#define MPG_MATRIX_IDX_INTRA 0x00
#define MPG_MATRIX_IDX_NON 0x01
#define MPG_MATRIX_DATA 0x60
#define MPG_SLICE_CTRL_1 0x90
#define MPG_SLICE_MBAMAX 0x2FFF
#define MPG_SLICE_PREDICTIVE_DCT 0x4000
#define MPG_SLICE_TOP_FIRST 0x8000
#define MPG_SLICE_MACROBLOCK_WIDTH(x) ((x)<<18) /* in 64's */
#define MPG_SLICE_CTRL_2 0x94
#define MPG_SLICE_CONCEAL_MVEC 0x0000001
#define MPG_SLICE_QSCALE_TYPE 0x0000002
#define MPG_SLICE_DCPRECISION 0x000000C
#define MPG_SLICE_MACROBQUOT 0x0FFFFF0
#define MPG_SLICE_INTRAVLC 0x1000000
#define MPG_SLICE_CTRL_3 0x98
#define MPG_SLICE_FHMVR 0x0000003
#define MPG_SLICE_FVMVR 0x000000C
#define MPG_SLICE_BHMVR 0x0000030
#define MPG_SLICE_BVMVR 0x00000C0
#define MPG_SLICE_SECOND_FIELD 0x0100000
#define MPG_SLICE_RESET 0x0400000
#define MPG_SLICE_LENGTH 0x9C
#define MPG_SLICE_DATA 0xA0
#endif /* _VIA_H_ */

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vidix/drivers/unichrome_vid.c Normal file
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@ -0,0 +1,945 @@
/*
Driver for VIA CLE266 Unichrome - Version 0.1.0
Copyright (C) 2004 by Timothy Lee
Based on Cyberblade/i driver by Alastair M. Robison.
Thanks to Gilles Frattini for bugfixes
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
Changes:
2004-03-10
Initial version
2004-10-09
Added Doxygen documentation (Benjamin Zores <ben@geexbox.org>)
To Do:
*/
#include <errno.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <inttypes.h>
#include <unistd.h>
#include "../vidix.h"
#include "../fourcc.h"
#include "../../libdha/libdha.h"
#include "../../libdha/pci_ids.h"
#include "../../libdha/pci_names.h"
#include "../../config.h"
#include "unichrome_regs.h"
/**
* @brief Information on PCI device.
*/
pciinfo_t pci_info;
/**
* @brief Unichrome driver colorkey settings.
*/
static vidix_grkey_t uc_grkey;
static int frames[VID_PLAY_MAXFRAMES];
uint8_t *vio;
uint8_t *uc_mem;
uint8_t mclk_save[3];
#define VIA_OUT(hwregs, reg, val) *(volatile uint32_t *)((hwregs) + (reg)) = (val)
#define VIA_IN(hwregs, reg) *(volatile uint32_t *)((hwregs) + (reg))
#define VGA_OUT8(hwregs, reg, val) *(volatile uint8_t *)((hwregs) + (reg) + 0x8000) = (val)
#define VGA_IN8(hwregs, reg) *(volatile uint8_t *)((hwregs) + (reg) + 0x8000)
#define VIDEO_OUT(hwregs, reg, val) VIA_OUT((hwregs)+0x200, reg, val)
#define VIDEO_IN(hwregs, reg) VIA_IN((hwregs)+0x200, reg)
#define outb(val,reg) OUTPORT8(reg,val)
#define inb(reg) INPORT8(reg)
#define ALIGN_TO(v, n) (((v) + (n-1)) & ~(n-1))
#define UC_MAP_V1_FIFO_CONTROL(depth, pre_thr, thr) \
(((depth)-1) | ((thr) << 8) | ((pre_thr) << 24))
#define FRAMEBUFFER_START 0x600000
#define FRAMEBUFFER_SIZE 0x200000
#ifdef DEBUG_LOGFILE
FILE *logfile = 0;
#define LOGWRITE(x) {if(logfile) fprintf(logfile,x);}
#else
#define LOGWRITE(x)
#endif
/**
* @brief Unichrome driver vidix capabilities.
*/
static vidix_capability_t uc_cap = {
"VIA CLE266 Unichrome driver",
"Timothy Lee <timothy@siriushk.com>",
TYPE_OUTPUT,
{0, 0, 0, 0},
4096,
4096,
4,
4,
-1,
FLAG_UPSCALER | FLAG_DOWNSCALER,
VENDOR_VIA2,
-1,
{0, 0, 0, 0}
};
/**
* @brief list of card IDs compliant with the Unichrome driver .
*/
static unsigned short uc_card_ids[] = {
DEVICE_VIA2_VT8623_CLE266_AGP
};
/**
* @brief Check age of driver.
*
* @return vidix version number.
*/
unsigned int
vixGetVersion (void)
{
return (VIDIX_VERSION);
}
/**
* @brief Find chip index in Unichrome compliant devices list.
*
* @param chip_id PCI device ID.
*
* @returns index position in uc_card_ids if successful.
* -1 if chip_id is not a compliant chipset ID.
*/
static int
find_chip (unsigned chip_id)
{
unsigned i;
for (i = 0; i < sizeof (uc_card_ids) / sizeof (unsigned short); i++)
{
if (chip_id == uc_card_ids[i])
return i;
}
return -1;
}
/**
* @brief Map hardware settings for vertical scaling.
*
* @param sh source height.
* @param dh destination height.
* @param zoom will hold vertical setting of zoom register.
* @param mini will hold vertical setting of mini register.
*
* @returns 1 if successful.
* 0 if the zooming factor is too large or small.
*
* @note Derived from VIA's V4L driver.
* See ddover.c, DDOVER_HQVCalcZoomHeight()
*/
int
uc_ovl_map_vzoom (int sh, int dh, uint32_t * zoom, uint32_t * mini)
{
uint32_t sh1, tmp, d;
int zoom_ok = 1;
if (sh == dh) /* No zoom */
{
/* Do nothing */
}
else if (sh < dh) /* Zoom in */
{
tmp = (sh * 0x0400) / dh;
zoom_ok = !(tmp > 0x3ff);
*zoom |= (tmp & 0x3ff) | V1_Y_ZOOM_ENABLE;
*mini |= V1_Y_INTERPOLY | V1_YCBCR_INTERPOLY;
}
else /* sw > dh - Zoom out */
{
/* Find a suitable divider (1 << d) = {2, 4, 8 or 16} */
sh1 = sh;
for (d = 1; d < 5; d++)
{
sh1 >>= 1;
if (sh1 <= dh)
break;
}
if (d == 5) /* too small */
{
d = 4;
zoom_ok = 0;
}
*mini |= ((d << 1) - 1) << 16; /* <= {1,3,5,7} << 16 */
/* Add scaling */
if (sh1 < dh)
{
tmp = (sh1 * 0x400) / dh;
*zoom |= ((tmp & 0x3ff) | V1_Y_ZOOM_ENABLE);
*mini |= V1_Y_INTERPOLY | V1_YCBCR_INTERPOLY;
}
}
return zoom_ok;
}
/**
* @brief Map hardware settings for horizontal scaling.
*
* @param sw source width.
* @param dw destination width.
* @param zoom will hold horizontal setting of zoom register.
* @param mini will hold horizontal setting of mini register.
* @param falign will hold fetch aligment.
* @param dcount will hold display count.
*
* @returns 1 if successful.
* 0 if the zooming factor is too large or small.
*
* @note Derived from VIA's V4L driver.
* See ddover.c, DDOVER_HQVCalcZoomWidth() and DDOver_GetDisplayCount()
*/
int
uc_ovl_map_hzoom (int sw, int dw, uint32_t * zoom, uint32_t * mini,
int *falign, int *dcount)
{
uint32_t tmp, sw1, d;
int md; /* Minify-divider */
int zoom_ok = 1;
md = 1;
*falign = 0;
if (sw == dw) /* no zoom */
{
/* Do nothing */
}
else if (sw < dw) /* zoom in */
{
tmp = (sw * 0x0800) / dw;
zoom_ok = !(tmp > 0x7ff);
*zoom |= ((tmp & 0x7ff) << 16) | V1_X_ZOOM_ENABLE;
*mini |= V1_X_INTERPOLY;
}
else /* sw > dw - Zoom out */
{
/* Find a suitable divider (1 << d) = {2, 4, 8 or 16} */
sw1 = sw;
for (d = 1; d < 5; d++)
{
sw1 >>= 1;
if (sw1 <= dw)
break;
}
if (d == 5) /* too small */
{
d = 4;
zoom_ok = 0;
}
md = 1 << d; /* <= {2,4,8,16} */
*falign = ((md << 1) - 1) & 0xf; /* <= {3,7,15,15} */
*mini |= V1_X_INTERPOLY;
*mini |= ((d << 1) - 1) << 24; /* <= {1,3,5,7} << 24 */
/* Add scaling */
if (sw1 < dw)
{
/* CLE bug */
/* tmp = sw1*0x0800 / dw; */
tmp = (sw1 - 2) * 0x0800 / dw;
*zoom |= ((tmp & 0x7ff) << 16) | V1_X_ZOOM_ENABLE;
}
}
*dcount = sw - md;
return zoom_ok;
}
/**
* @brief qword fetch register setting.
*
* @param format overlay pixel format.
* @param sw source width.
*
* @return qword fetch register setting
*
* @note Derived from VIA's V4L driver. See ddover.c, DDOver_GetFetch()
* @note Only call after uc_ovl_map_hzoom()
*/
uint32_t
uc_ovl_map_qwfetch (uint32_t format, int sw)
{
uint32_t fetch = 0;
switch (format)
{
case IMGFMT_YV12:
case IMGFMT_I420:
fetch = ALIGN_TO (sw, 32) >> 4;
break;
case IMGFMT_UYVY:
case IMGFMT_YVYU:
case IMGFMT_YUY2:
fetch = (ALIGN_TO (sw << 1, 16) >> 4) + 1;
break;
case IMGFMT_BGR15:
case IMGFMT_BGR16:
fetch = (ALIGN_TO (sw << 1, 16) >> 4) + 1;
break;
case IMGFMT_BGR32:
fetch = (ALIGN_TO (sw << 2, 16) >> 4) + 1;
break;
default:
printf ("[unichrome] Unexpected pixelformat!");
break;
}
if (fetch < 4)
fetch = 4;
return fetch;
}
/**
* @brief Map pixel format.
*
* @param format pixel format.
*
* @return the mapped pixel format.
*
* @note Derived from VIA's V4L driver. See ddover.c, DDOver_GetV1Format()
*/
uint32_t
uc_ovl_map_format (uint32_t format)
{
switch (format)
{
case IMGFMT_UYVY:
case IMGFMT_YVYU:
case IMGFMT_YUY2:
return V1_COLORSPACE_SIGN | V1_YUV422;
case IMGFMT_IYUV:
return V1_COLORSPACE_SIGN | V1_YCbCr420 | V1_SWAP_SW;
case IMGFMT_YV12:
case IMGFMT_I420:
return V1_COLORSPACE_SIGN | V1_YCbCr420;
case IMGFMT_BGR15:
return V1_RGB15;
case IMGFMT_BGR16:
return V1_RGB16;
case IMGFMT_BGR32:
return V1_RGB32;
default:
printf ("[unichrome] Unexpected pixelformat!");
return V1_YUV422;
}
}
/**
* @brief Calculate V1 control and fifo-control register values.
*
* @param format pixel format.
* @param sw source width.
* @param hwrev CLE266 hardware revision.
* @param extfifo_on set this 1 if the extended FIFO is enabled.
* @param control will hold value for V1_CONTROL.
* @param fifo will hold value for V1_FIFO_CONTROL.
*/
void
uc_ovl_map_v1_control (uint32_t format, int sw,
int hwrev, int extfifo_on,
uint32_t * control, uint32_t * fifo)
{
*control = V1_BOB_ENABLE | uc_ovl_map_format (format);
if (hwrev == 0x10)
{
*control |= V1_EXPIRE_NUM_F;
}
else
{
if (extfifo_on)
{
*control |= V1_EXPIRE_NUM_A | V1_FIFO_EXTENDED;
}
else
{
*control |= V1_EXPIRE_NUM;
}
}
if ((format == IMGFMT_YV12) || (format == IMGFMT_I420))
{
/* Minified video will be skewed without this workaround. */
if (sw <= 80) /* Fetch count <= 5 */
{
*fifo = UC_MAP_V1_FIFO_CONTROL (16, 0, 0);
}
else
{
if (hwrev == 0x10)
*fifo = UC_MAP_V1_FIFO_CONTROL (64, 56, 56);
else
*fifo = UC_MAP_V1_FIFO_CONTROL (16, 12, 8);
}
}
else
{
if (hwrev == 0x10)
{
*fifo = UC_MAP_V1_FIFO_CONTROL (64, 56, 56); /* Default rev 0x10 */
}
else
{
if (extfifo_on)
*fifo = UC_MAP_V1_FIFO_CONTROL (48, 40, 40);
else
*fifo = UC_MAP_V1_FIFO_CONTROL (32, 29, 16); /* Default */
}
}
}
/**
* @brief Setup extended FIFO.
*
* @param extfifo_on pointer determining if extended fifo is enable or not.
* @param dst_w destination width.
*/
void
uc_ovl_setup_fifo (int *extfifo_on, int dst_w)
{
if (dst_w <= 1024) /* Disable extended FIFO */
{
outb (0x16, 0x3c4);
outb (mclk_save[0], 0x3c5);
outb (0x17, 0x3c4);
outb (mclk_save[1], 0x3c5);
outb (0x18, 0x3c4);
outb (mclk_save[2], 0x3c5);
*extfifo_on = 0;
}
else /* Enable extended FIFO */
{
outb (0x17, 0x3c4);
outb (0x2f, 0x3c5);
outb (0x16, 0x3c4);
outb ((mclk_save[0] & 0xf0) | 0x14, 0x3c5);
outb (0x18, 0x3c4);
outb (0x56, 0x3c5);
*extfifo_on = 1;
}
}
void
uc_ovl_vcmd_wait (volatile uint8_t * vio)
{
while ((VIDEO_IN (vio, V_COMPOSE_MODE)
& (V1_COMMAND_FIRE | V3_COMMAND_FIRE)));
}
/**
* @brief Probe hardware to find some useable chipset.
*
* @param verbose specifies verbose level.
* @param force specifies force mode : driver should ignore
* device_id (danger but useful for new devices)
*
* @returns 0 if it can handle something in PC.
* a negative error code otherwise.
*/
int
vixProbe (int verbose, int force)
{
pciinfo_t lst[MAX_PCI_DEVICES];
unsigned i, num_pci;
int err;
err = pci_scan (lst, &num_pci);
if (err)
{
printf ("[unichrome] Error occurred during pci scan: %s\n",
strerror (err));
return err;
}
else
{
err = ENXIO;
for (i = 0; i < num_pci; i++)
{
if (lst[i].vendor == VENDOR_VIA2)
{
int idx;
const char *dname;
idx = find_chip (lst[i].device);
if (idx == -1)
continue;
dname = pci_device_name (VENDOR_VIA2, lst[i].device);
dname = dname ? dname : "Unknown chip";
printf ("[unichrome] Found chip: %s\n", dname);
if ((lst[i].command & PCI_COMMAND_IO) == 0)
{
printf ("[unichrome] Device is disabled, ignoring\n");
continue;
}
uc_cap.device_id = lst[i].device;
err = 0;
memcpy (&pci_info, &lst[i], sizeof (pciinfo_t));
break;
}
}
}
if (err && verbose)
printf ("[unichrome] Can't find chip\n");
return err;
}
/**
* @brief Initializes driver.
*
* @returns 0 if ok.
* a negative error code otherwise.
*/
int
vixInit (void)
{
long tmp;
uc_mem = map_phys_mem (pci_info.base0, 0x800000);
enable_app_io ();
outb (0x2f, 0x3c4);
tmp = inb (0x3c5) << 0x18;
vio = map_phys_mem (tmp, 0x1000);
outb (0x16, 0x3c4);
mclk_save[0] = inb (0x3c5);
outb (0x17, 0x3c4);
mclk_save[1] = inb (0x3c5);
outb (0x18, 0x3c4);
mclk_save[2] = inb (0x3c5);
uc_grkey.ckey.blue = 0x00;
uc_grkey.ckey.green = 0x00;
uc_grkey.ckey.red = 0x00;
#ifdef DEBUG_LOGFILE
logfile = fopen ("/tmp/uc_vidix.log", "w");
#endif
return 0;
}
/**
* @brief Destroys driver.
*/
void
vixDestroy (void)
{
#ifdef DEBUG_LOGFILE
if (logfile)
fclose (logfile);
#endif
outb (0x16, 0x3c4);
outb (mclk_save[0], 0x3c5);
outb (0x17, 0x3c4);
outb (mclk_save[1], 0x3c5);
outb (0x18, 0x3c4);
outb (mclk_save[2], 0x3c5);
disable_app_io ();
unmap_phys_mem (uc_mem, 0x800000);
unmap_phys_mem (vio, 0x1000);
}
/**
* @brief Get chipset's hardware capabilities.
*
* @param to Pointer to the vidix_capability_t structure to be filled.
*
* @returns 0.
*/
int
vixGetCapability (vidix_capability_t * to)
{
memcpy (to, &uc_cap, sizeof (vidix_capability_t));
return 0;
}
/**
* @brief Report if the video FourCC is supported by hardware.
*
* @param fourcc input image format.
*
* @returns 1 if the fourcc is supported.
* 0 otherwise.
*/
static int
is_supported_fourcc (uint32_t fourcc)
{
switch (fourcc)
{
case IMGFMT_YV12:
case IMGFMT_I420:
case IMGFMT_UYVY:
case IMGFMT_YVYU:
case IMGFMT_YUY2:
case IMGFMT_BGR15:
case IMGFMT_BGR16:
case IMGFMT_BGR32:
return 1;
default:
return 0;
}
}
/**
* @brief Try to configure video memory for given fourcc.
*
* @param to Pointer to the vidix_fourcc_t structure to be filled.
*
* @returns 0 if ok.
* errno otherwise.
*/
int
vixQueryFourcc (vidix_fourcc_t * to)
{
if (is_supported_fourcc (to->fourcc))
{
to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP |
VID_DEPTH_4BPP | VID_DEPTH_8BPP |
VID_DEPTH_12BPP | VID_DEPTH_15BPP |
VID_DEPTH_16BPP | VID_DEPTH_24BPP | VID_DEPTH_32BPP;
to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY;
return 0;
}
else
to->depth = to->flags = 0;
return ENOSYS;
}
/**
* @brief Get the GrKeys
*
* @param grkey Pointer to the vidix_grkey_t structure to be filled by driver.
*
* @return 0.
*/
int
vixGetGrKeys (vidix_grkey_t * grkey)
{
memcpy (grkey, &uc_grkey, sizeof (vidix_grkey_t));
return (0);
}
/**
* @brief Set the GrKeys
*
* @param grkey Colorkey to be set.
*
* @return 0.
*/
int
vixSetGrKeys (const vidix_grkey_t * grkey)
{
unsigned long dwCompose = VIDEO_IN (vio, V_COMPOSE_MODE) & ~0x0f;
memcpy (&uc_grkey, grkey, sizeof (vidix_grkey_t));
if (uc_grkey.ckey.op != CKEY_FALSE)
{
/* Set colorkey (how do I detect BPP in hardware ??) */
unsigned long ckey;
if (1) /* Assume 16-bit graphics */
{
ckey = (grkey->ckey.blue & 0x1f)
| ((grkey->ckey.green & 0x3f) << 5)
| ((grkey->ckey.red & 0x1f) << 11);
}
else
{
ckey = (grkey->ckey.blue)
| (grkey->ckey.green << 8) | (grkey->ckey.red << 16);
}
VIDEO_OUT (vio, V_COLOR_KEY, ckey);
dwCompose |= SELECT_VIDEO_IF_COLOR_KEY;
}
/* Execute the changes */
VIDEO_OUT (vio, V_COMPOSE_MODE, dwCompose | V1_COMMAND_FIRE);
return (0);
}
/**
* @brief Unichrome driver equalizer capabilities.
*/
vidix_video_eq_t equal = {
VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION | VEQ_CAP_HUE,
300, 100, 0, 0, 0, 0, 0, 0
};
/**
* @brief Get the equalizer capabilities.
*
* @param eq Pointer to the vidix_video_eq_t structure to be filled by driver.
*
* @return 0.
*/
int
vixPlaybackGetEq (vidix_video_eq_t * eq)
{
memcpy (eq, &equal, sizeof (vidix_video_eq_t));
return 0;
}
/**
* @brief Set the equalizer capabilities for color correction
*
* @param eq equalizer capabilities to be set.
*
* @return 0.
*/
int
vixPlaybackSetEq (const vidix_video_eq_t * eq)
{
return 0;
}
/**
* @brief Y, U, V offsets.
*/
static int YOffs, UOffs, VOffs;
/**
* @brief Configure driver for playback. Driver should prepare BES.
*
* @param info configuration description for playback.
*
* @returns 0 in case of success.
* -1 otherwise.
*/
int
vixConfigPlayback (vidix_playback_t * info)
{
int src_w, drw_w;
int src_h, drw_h;
long base0, pitch;
int uv_size, swap_uv;
unsigned int i;
int extfifo_on;
/* Overlay register settings */
uint32_t win_start, win_end;
uint32_t zoom, mini;
uint32_t dcount, falign, qwfetch;
uint32_t y_start, u_start, v_start;
uint32_t v_ctrl, fifo_ctrl;
if (!is_supported_fourcc (info->fourcc))
return -1;
src_w = info->src.w;
src_h = info->src.h;
drw_w = info->dest.w;
drw_h = info->dest.h;
/* Setup FIFO */
uc_ovl_setup_fifo (&extfifo_on, src_w);
/* Get image format, FIFO size, etc. */
uc_ovl_map_v1_control (info->fourcc, src_w, 3, extfifo_on,
&v_ctrl, &fifo_ctrl);
/* Setup layer window */
win_start = (info->dest.x << 16) | info->dest.y;
win_end = ((info->dest.x + drw_w - 1) << 16) | (info->dest.y + drw_h - 1);
/* Get scaling and data-fetch parameters */
zoom = 0;
mini = 0;
uc_ovl_map_vzoom (src_h, drw_h, &zoom, &mini);
uc_ovl_map_hzoom (src_w, drw_w, &zoom, &mini, &falign, &dcount);
qwfetch = uc_ovl_map_qwfetch (info->fourcc, src_w);
/* Calculate buffer sizes */
swap_uv = 0;
switch (info->fourcc)
{
case IMGFMT_YV12:
swap_uv = 1;
case IMGFMT_I420:
case IMGFMT_UYVY:
case IMGFMT_YVYU:
pitch = ALIGN_TO (src_w, 32);
uv_size = (pitch >> 1) * (src_h >> 1);
break;
case IMGFMT_YUY2:
case IMGFMT_BGR15:
case IMGFMT_BGR16:
pitch = ALIGN_TO (src_w << 1, 32);
uv_size = 0;
break;
case IMGFMT_BGR32:
pitch = ALIGN_TO (src_w << 2, 32);
uv_size = 0;
break;
}
if ((src_w > 4096) || (src_h > 4096) ||
(src_w < 32) || (src_h < 1) || (pitch > 0x1fff))
{
printf ("[unichrome] Layer size out of bounds\n");
}
/* Calculate offsets */
info->offset.y = 0;
info->offset.v = info->offset.y + pitch * src_h;
info->offset.u = info->offset.v + uv_size;
info->frame_size = info->offset.u + uv_size;
YOffs = info->offset.y;
UOffs = (swap_uv ? info->offset.v : info->offset.u);
VOffs = (swap_uv ? info->offset.u : info->offset.v);
/* Assume we have 2 MB to play with */
info->num_frames = FRAMEBUFFER_SIZE / info->frame_size;
if (info->num_frames > VID_PLAY_MAXFRAMES)
info->num_frames = VID_PLAY_MAXFRAMES;
/* Start at 6 MB. Let's hope it's not in use. */
base0 = FRAMEBUFFER_START;
info->dga_addr = uc_mem + base0;
info->dest.pitch.y = 32;
info->dest.pitch.u = 32;
info->dest.pitch.v = 32;
for (i = 0; i < info->num_frames; i++)
{
info->offsets[i] = info->frame_size * i;
frames[i] = base0 + info->offsets[i];
}
/* Write to the hardware */
uc_ovl_vcmd_wait (vio);
/* Configure diy_pitchlay parameters now */
if (v_ctrl & V1_COLORSPACE_SIGN)
{
VIDEO_OUT (vio, V1_ColorSpaceReg_2, ColorSpaceValue_2);
VIDEO_OUT (vio, V1_ColorSpaceReg_1, ColorSpaceValue_1);
}
VIDEO_OUT (vio, V1_CONTROL, v_ctrl);
VIDEO_OUT (vio, V_FIFO_CONTROL, fifo_ctrl);
VIDEO_OUT (vio, V1_WIN_START_Y, win_start);
VIDEO_OUT (vio, V1_WIN_END_Y, win_end);
VIDEO_OUT (vio, V1_SOURCE_HEIGHT, (src_h << 16) | dcount);
VIDEO_OUT (vio, V12_QWORD_PER_LINE, qwfetch << 20);
VIDEO_OUT (vio, V1_STRIDE, pitch | ((pitch >> 1) << 16));
VIDEO_OUT (vio, V1_MINI_CONTROL, mini);
VIDEO_OUT (vio, V1_ZOOM_CONTROL, zoom);
/* Configure buffer address and execute the changes now! */
vixPlaybackFrameSelect (0);
return 0;
}
/**
* @brief Set playback on : driver should activate BES on this call.
*
* @return 0.
*/
int
vixPlaybackOn (void)
{
LOGWRITE ("Enable overlay\n");
/* Turn on overlay */
VIDEO_OUT (vio, V1_CONTROL, VIDEO_IN (vio, V1_CONTROL) | V1_ENABLE);
/* Execute the changes */
VIDEO_OUT (vio, V_COMPOSE_MODE,
VIDEO_IN (vio, V_COMPOSE_MODE) | V1_COMMAND_FIRE);
return 0;
}
/**
* @brief Set playback off : driver should deactivate BES on this call.
*
* @return 0.
*/
int
vixPlaybackOff (void)
{
LOGWRITE ("Disable overlay\n");
uc_ovl_vcmd_wait (vio);
/* Restore FIFO */
VIDEO_OUT (vio, V_FIFO_CONTROL, UC_MAP_V1_FIFO_CONTROL (16, 12, 8));
/* Turn off overlay */
VIDEO_OUT (vio, V1_CONTROL, VIDEO_IN (vio, V1_CONTROL) & ~V1_ENABLE);
/* Execute the changes */
VIDEO_OUT (vio, V_COMPOSE_MODE,
VIDEO_IN (vio, V_COMPOSE_MODE) | V1_COMMAND_FIRE);
return 0;
}
/**
* @brief Driver should prepare and activate corresponded frame.
*
* @param frame the frame index.
*
* @return 0.
*
* @note This function is used only for double and triple buffering
* and never used for single buffering playback.
*/
int
vixPlaybackFrameSelect (unsigned int frame)
{
LOGWRITE ("Frame select\n");
uc_ovl_vcmd_wait (vio);
/* Configure buffer address */
VIDEO_OUT (vio, V1_STARTADDR_Y0, frames[frame] + YOffs);
VIDEO_OUT (vio, V1_STARTADDR_CB0, frames[frame] + UOffs);
VIDEO_OUT (vio, V1_STARTADDR_CR0, frames[frame] + VOffs);
/* Execute the changes */
VIDEO_OUT (vio, V_COMPOSE_MODE,
VIDEO_IN (vio, V_COMPOSE_MODE) | V1_COMMAND_FIRE);
return 0;
}