mirror of
https://github.com/mpv-player/mpv.git
synced 2024-09-20 20:03:10 +02:00
+ Added support of FIFO engine (suggested by Vladimir Dergachev)
- Disabled save/restore state functions (caused a lots of problems during driver reloading) git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@3608 b3059339-0415-0410-9bf9-f77b7e298cf2
This commit is contained in:
nick
parent
3be3ff7ef3
commit
a0a14b6c67
@ -17,7 +17,7 @@
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* Rage128(pro) stuff of this driver.
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*/
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#define RADEON_VID_VERSION "1.1.1"
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#define RADEON_VID_VERSION "1.1.2"
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/*
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It's entirely possible this major conflicts with something else
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@ -180,7 +180,7 @@ static bes_registers_t besr;
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#else
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#define DECLARE_VREG(name) { name, 0 }
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#endif
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#ifdef DEBUG
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static video_registers_t vregs[] =
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{
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DECLARE_VREG(VIDEOMUX_CNTL),
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@ -275,7 +275,7 @@ static video_registers_t vregs[] =
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DECLARE_VREG(IDCT_AUTH),
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DECLARE_VREG(IDCT_CONTROL)
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};
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#endif
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static uint32_t radeon_vid_in_use = 0;
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static uint8_t *radeon_mmio_base = 0;
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@ -344,6 +344,13 @@ static char *fourcc_format_name(int format)
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#define OUTREG8(addr,val) writeb(val, (radeon_mmio_base)+addr)
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#define INREG(addr) readl((radeon_mmio_base)+addr)
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#define OUTREG(addr,val) writel(val, (radeon_mmio_base)+addr)
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#define OUTREGP(addr,val,mask) \
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do { \
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unsigned int _tmp = INREG(addr); \
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_tmp &= (mask); \
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_tmp |= (val); \
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OUTREG(addr, _tmp); \
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} while (0)
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static uint32_t radeon_vid_get_dbpp( void )
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{
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@ -370,6 +377,50 @@ static int radeon_is_interlace( void )
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return (INREG(CRTC_GEN_CNTL))&CRTC_INTERLACE_EN;
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}
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static __inline__ void radeon_engine_flush ( void )
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{
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int i;
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/* initiate flush */
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OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
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~RB2D_DC_FLUSH_ALL);
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for (i=0; i < 2000000; i++) {
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if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
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break;
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}
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}
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static __inline__ void _radeon_fifo_wait (int entries)
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{
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int i;
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for (i=0; i<2000000; i++)
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if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
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return;
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}
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static __inline__ void _radeon_engine_idle ( void )
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{
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int i;
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/* ensure FIFO is empty before waiting for idle */
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_radeon_fifo_wait (64);
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for (i=0; i<2000000; i++) {
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if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
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radeon_engine_flush ();
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return;
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}
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}
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}
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#define radeon_engine_idle() _radeon_engine_idle()
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#define radeon_fifo_wait(entries) _radeon_fifo_wait(entries)
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#if 0
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static void __init radeon_vid_save_state( void )
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{
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size_t i;
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@ -380,10 +431,19 @@ static void __init radeon_vid_save_state( void )
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static void __exit radeon_vid_restore_state( void )
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{
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size_t i;
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radeon_fifo_wait(2);
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OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK);
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radeon_engine_idle();
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while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK));
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radeon_fifo_wait(15);
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for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++)
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{
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radeon_fifo_wait(1);
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OUTREG(vregs[i].name,vregs[i].value);
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}
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OUTREG(OV0_REG_LOAD_CNTL, 0);
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}
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#endif
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#ifdef DEBUG
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static void radeon_vid_dump_regs( void )
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{
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@ -397,6 +457,7 @@ static void radeon_vid_dump_regs( void )
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static void radeon_vid_stop_video( void )
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{
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radeon_engine_idle();
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OUTREG(OV0_SCALE_CNTL, SCALER_SOFT_RESET);
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OUTREG(OV0_EXCLUSIVE_HORZ, 0);
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OUTREG(OV0_AUTO_FLIP_CNTL, 0); /* maybe */
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@ -408,9 +469,11 @@ static void radeon_vid_stop_video( void )
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static void radeon_vid_display_video( void )
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{
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int bes_flags;
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radeon_fifo_wait(2);
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OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK);
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radeon_engine_idle();
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while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK));
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radeon_fifo_wait(15);
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OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD);
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OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE));
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OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE));
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@ -421,6 +484,7 @@ static void radeon_vid_display_video( void )
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(besr.saturation << 8) |
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(besr.saturation << 16));
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#endif
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radeon_fifo_wait(2);
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if(besr.ckey_on)
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{
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OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk);
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@ -452,6 +516,7 @@ static void radeon_vid_display_video( void )
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OUTREG(OV0_VID_BUF0_BASE_ADRS, besr.vid_buf0_base_adrs);
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OUTREG(OV0_VID_BUF1_BASE_ADRS, besr.vid_buf1_base_adrs);
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OUTREG(OV0_VID_BUF2_BASE_ADRS, besr.vid_buf2_base_adrs);
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radeon_fifo_wait(9);
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OUTREG(OV0_VID_BUF3_BASE_ADRS, besr.vid_buf3_base_adrs);
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OUTREG(OV0_VID_BUF4_BASE_ADRS, besr.vid_buf4_base_adrs);
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OUTREG(OV0_VID_BUF5_BASE_ADRS, besr.vid_buf5_base_adrs);
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@ -1135,7 +1200,9 @@ static int __init radeon_vid_initialize(void)
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}
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radeon_param_buff = kmalloc(PARAM_BUFF_SIZE,GFP_KERNEL);
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if(radeon_param_buff) radeon_param_buff_size = PARAM_BUFF_SIZE;
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#if 0
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radeon_vid_save_state();
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#endif
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radeon_vid_make_default();
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radeon_vid_preset();
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#ifdef CONFIG_MTRR
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@ -1157,7 +1224,9 @@ int __init init_module(void)
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void __exit cleanup_module(void)
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{
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#if 0
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radeon_vid_restore_state();
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#endif
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if(radeon_mmio_base)
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iounmap(radeon_mmio_base);
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kfree(radeon_param_buff);
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